`timescale 1ns / 1ps

module MUX_TB;

    // Inputs
    reg clk;
    wire a;
    wire b;
    wire c;
    wire d;
    reg [1:0] sel;
    reg [3:0] inputs_lines;
    // Outputs
    wire [1:0] out;
    integer i, j;
    
MU_4to1 uut (
    .clk_in(clk), 
    .a_in(a), 
    .b_in(b), 
    .c_in(c), 
    .d_in(d), 
    .sel_in(sel), 
    .out(out)
);

assign {a,b,c,d} = inputs_lines;

initial begin
    inputs_lines = 0;
    sel = 0;
    for (i=0;i<4;i=i+1) begin
        for (j=0;j<16;j=j+1) begin
            inputs_lines =inputs_lines+1;
            @(posedge uut.clk);
        end
        sel <= sel+1;
    end
end

initial begin 
    clk = 0;
    forever begin
        #10;
        clk = ~clk;
    end
end
endmodule